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Features
* * * * * * * * * * * * * * *
Main Supply 3.0V to 3.6V Independent 2.5V to 3.6V Auxiliary Supply for Backup Section Internal State Machine for Startup 25 mA/1.8V-2.75V Linear Low Drop Out Regulator with High PSRR and Low Noise (LDO1) 30 mA/1.5V-1.8V Linear Low Drop Out Regulator with High PSRR and Low Noise (LDO2) 60 mA/1.23V-1.5V-1.8V Linear Low Drop Out Regulator with High PSRR (LDO3) 2 mA/1.2V-1.5V-1.8V Linear Low Drop Out Regulator with Very Low Quiescent Current (LDO4) HPBG Economic High Performance Voltage Reference for LDO Supply to RF Sections LPBG Low Power Voltage Reference to LDO4 During Backup Battery Operation Internal Oscillator Generates Internal Master Clock Internal Reset Generator for Main Supply Additional External Reset Input Two Wire Interface (TWI) for Independent Activation and Output Voltage Programming for Each LDO Available in 3 x 3 x 0.9 mm 16-pin QFN Package Applications: GPS Modules, WLAN Devices, Wireless Modules
Power Management and Analog Companions (PMAAC) AT73C239 4-channel Power Management for Wireless Modules
1. Description
The AT73C239 is a four-channel Power Supply Power Management Unit (PMU) available in a QFN 3 x 3 mm package. It is a fully integrated, low cost, combined Power Management device for wireless modules, GPS and WLAN devices. It integrates four Linear Low Drop Out (LDO) Regulators, three of which provide high-accuracy RF performance and one (LDO4) with very low quiescent current that is supplied by an external backup battery. A Low Power Bandgap (LPBG) requiring no external capacitor for decoupling, is used as reference voltage for LDO4 and starts when VBAT is present. LDO4 regulates output voltage with extremely low quiescent current, maximizing the lifetime of the backup battery. An Internal State Machine manages the startup of the other LDOs in the order of LDO3 then LDO1 then LDO2. An economic High Power Bandgap (HPBG) provides highly accurate, low noise voltage reference to LDOs 1, 2, 3. HPBG operates in switching mode thereby decreasing its current consumption and becomes inactive when not directly supplied by VIN current. When the RF LDOs are in idle mode, quiescent current is decreased to a minimum. The AT73C239 features a Two-wire Interface (TWI) to increase the efficiency of the system by disabling LDOs when not needed.
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2. Block Diagram
Figure 2-1. AT73C239 Functional Block Diagram
VDD1
LDO1 VBG HPBG VDD 3.0V-3.6V VOUT 1.8V or 2.75V ILOAD 25 mA Internal Oscillator
GNDA/AVSS
VO1
XRESIN XRESO TWCK TWD GNDD LDO2 Reset Generator TWI State Machine VDD 3.0V-3.6V VOUT 1.5V or 1.8V ILOAD 30 mA
VDD2
VO2
Fuse1 VZAP
Fuse2
VMON
POR1 VBAT
POR1 VDD3
LDO4 VDD 2.5V-3.6V VOUT 1.2V or 1.5V or 1.8V
LDO3 VDD 3.0V-3.6V VOUT 1.23V or 1.5V or 1.8V ILOAD 60 mA VO3
VO4
ILOAD 2 mA
LPBG
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3. Pin Description
Table 3-1. Pin Description
I/O Input Output Input Output Output GND Input input Input Output
(2)
Pin Name XRESIN VO3 VDD3 XRESO VO4 GNDD VBAT VZAP
(1)
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Type Digital Analog Power Digital Analog Power Power Digital Power Analog Digital Digital Power Analog Analog Analog
Function Reset in pin LDO3 output voltage LDO3 input voltage Reset out pin LDO4 output voltage Digital ground LDO4 input voltage Reserved for manufacturing purposes. LDO2 input voltage LDO2 output voltage TWI input TWI input/output LDO1 input voltage LDO1 output voltage Analog ground and ESD ground Voltage reference for analog cells
VDD2 VO2 TWICK TWID
Input Input/Output Input Output GND/Input Output
(3)
VDD1 VO1 GNDA/AVSS VBG Notes:
1. Connected to ground. 2. Connected to VDD1, 2, 3 if TWI is not used. 3. Connected to VDD1, 2, 3 if TWI is not used.
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4. Package
4.1 16-pin QFN Package Outline
Figure 4-1 shows the orientation of the 16-pin QFN package. Figure 4-1. 16-pin QFN Package - Bottom View
13 14 15 16
12 11 10 9 8 7 6 5
1 2 3 4
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5. Application Block Diagram
Figure 5-1. AT73C239 Application Block Diagram
AT73C239 CF VBG LDO1 VDD 3.0V-3.6V VOUT 1.8V or 2.7V VO1 Internal Oscillator ILOAD 25 mA COUT1 LDO2 Reset Generator TWI SM VDD 3.0V-3.6V VOUT 1.5V or 1.8V VO2 ILOAD 30 mA VIN VZAP VMON 3.0V Backup Battery (coin cell) POR1 VBAT 3.0V I/O Backup Supply CIN4 (1F) VBAT LDO4 VDD 2.5V-3.6V VOUT 1.2V or 1.5V or 1.8V 1.8V Backup Core COUT4 1.8 V Core VO4 ILOAD 2 mA LPBG ILOAD 60 mA COUT3 POR1 LDO3 VDD 3.0V-3.6V VOUT 1.2V or 1.5V or 1.8V VO3 VDD3 VIN to other regulators Fuse1 Fuse2 COUT2 VDD2 VIN LNA RF TCXO VDD1 VIN GPS Antenna CIN1
HPBG
GNDA/AVSS
XRESIN XRESO Baseband TWCK TWD GNDD
3.0V I/O Supply
CIN3 (1F)
VIN 3.3V
Main Supply
Table 5-1.
Application Schematic Reference and Pin Description
Pin VDD1 VDD2 VDD3 VBAT 1 F 20% Ceramic Capacitor, X5R VO1 VO2 VO3 VO4 VBG 100 nF, 20% Ceramic Capacitor Description
Schematic Reference CIN1 CIN2 CIN3 CIN4 COUT1 COUT2 COUT3 COUT4 CF
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6. Functional Description
The AT73C239 integrates the power supply channels described in this section.
6.1
LDO1
LDO1 is a 25 mA/1.8V-2.75V linear low drop out regulator with RF performance. LDO1 operates with supply from 3.0V to 3.6V and requires at least 300 mV of minimum drop-out. LDO1 supplies the RF section of wireless devices, showing high PSRR up to 100 kHz, and very low noise on wide frequency bandwidth. LDO1 requires a 1 F output capacitor. Figure 6-1. LDO1 Functional Diagram
VDD1 current reference VBG VIN
VO1
COUT1 overcurrent detection sel1 GNDA
onldo1 AVSS GNDA
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6.2 LDO2
LDO2 is a 30 mA/1.5V-1.8V linear low drop out regulator with RF performance. LDO2 operates with supply from 3.0V to 3.6V and needs at least 300 mV of minimum drop-out. LDO2supplies the RF section of wireless devices, showing high PSRR up to 100 kHz and very low noise on wide frequency bandwidth. LDO2 requires a 1 F output capacitor. Figure 6-2. LDO2 Functional Diagram
VDD2 current reference VBG VIN
VO2
COUT2 overcurrent detection sel2 GNDA
onldo2 AVSS GNDA
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6.3
LDO3
LDO3 is a 60 mA/1.2V or 1.5V or 1.8V linear low drop out regulator with RF performance. LDO3 operates with supply from 3.0V to 3.6V and needs at least 300 mV of minimum drop-out. LDO3 supplies the RF section of wireless devices, showing high PSRR up to 100 kHz and low noise on wide frequency bandwidth. LDO3 requires a 1 F output capacitor. Figure 6-3. LDO3 Functional Diagram
VDD3 current reference VBG VIN
VO3
COUT3 overcurrent detection sel3[1:0] GNDA
onldo3 AVSS GNDD
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6.4 LD04
LDO4 is a 2 mA/1.2V or 1.5V or 1.8V low drop out voltage regulator with very low quiescent current. LDO4 operates with supply from 2.5V to 3.6V and needs at least 300 mV of minimum dropout. LDO4 supplies the very low power section of the wireless baseband. It is usually supplied by the external backup battery and regulates voltage with very low quiescent current, maximizing the lifetime of the backup battery. LDO4 requires a 1 F output capacitor or 470 nF if the load is less than 250 A. LDO4 is always on once the battery is plugged in. The regulator is activated when POR1 is released. Figure 6-4. LDO4 Functional Diagram
VBATC VBAT
VBG
VO4
COUT4 sel4[1:0] trcore[1:0] GNDD
onldo4 AVSS GNDDC GNDA
6.5
High Performance Bandgap (HPBG)
HPBG provides highly accurate, low noise voltage reference to LDOs that supply RF sections. HPBG operates in switching mode, thus decreasing its current consumption. The economic High Performance Bandgap is particularly efficient when RF LDOs are in idle mode (output voltage provided with very low output current e.g. < 1 mA), as the RF section is not active and quiescent current must be decreased as much as possible. HPBG requires an external 100 nF ceramic capacitor to achieve very low noise high-accuracy voltage reference.
6.6
Low Power Bandgap (LPBG)
LPBG is used as reference voltage for LDO4. LPBG starts up as soon as the VBAT pin is active and does not require an external capacitor for decoupling.
6.7
Reset Generator
The reset generator produces output reset (XRSTOUT) at least 100 ms after input reset state is activated. Input reset state can be produced the following: * External manual reset connected to the XRESIN pin * Internal POR2 monitoring VIN (on VDD3 pin). POR2 is designed with a maximum threshold at 1.81V. XRESO pin can be generated only if VIN is present.
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6.8
Internal State Machine
The internal state machine manages the start up of the regulators connected to VDD1, VDD2 and VDD3 pins. The startup configuration is in the following order: 1. LDO3 2. LDO1 3. LDO2
6.9
Power on Reset on VBAT (POR1)
POR1 monitors the VBAT pin and generates an internal signal (VPOR1) to enable a fuse read operation for LDO4 output voltage programming and LDO4 startup. VPOR1 is released when VBAT is higher than 1.5V 300 mV.
6.10
Power on Reset on VDD3 (POR2)
POR2 monitors the VDD3 pin and generates an internal signal (VPOR2) to reset the internal State Machine and startup the Two-wire Interface (TWI). VPOR2 also enables the fuse read operation for LDO1, LDO2, LDO3 output voltage programming, reference voltage and internal oscillator trimming. VPOR2 is released when VIN is higher than 1.5V 300 mV.
6.11
Internal Oscillator
The internal oscillator generates the internal master clock to synchronize the state machine that monitors start up of the LDOs and controls HPBG.
6.12
Voltage Supply Monitor on VDD3 (VMON)
VMON monitors the VDD3 pin and generates an internal signal to enable the state machine to start up the LDOs and to generate the XRESO signal. Threshold is set to 2.7V at rising and 2.6V at shut down.
6.13
Two-wire Interface (TWI)
The TWI can be used to activate, disable and set the output voltage of the LDO1, 2, 3, 4 regulators. (VDD3 must be present in order for TWI to be used with LDO4.)
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7. Startup Procedure
At VBAT Rising: * LPBG automatically starts up. * POR1 starts up LDO4. At VDD3 Rising: * POR2 enables the following: - Supply Monitor with shutdown threshold setup at 2.7V in order to prevent corruption in the baseband chip, when the core is still supplied - Internal State machine that enables the other circuits according to the diagram shown in Figure 7-1 on page 12. - Two Wire Interface At VDD3 Falling: * The Supply Monitor generates a shut-down control signal when VDD3 reaches 2.6V. * The State Machine, upon receiving the shut-down control signal, generates the XRESO signal to set the baseband chip in reset mode. * The State Machine switches off LDO1, LDO2 and LDO3. HPBG is kept on in order to provide a fast startup of the LDOs in case of glitches on VDD3.
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7.1
Startup Diagram
Figure 7-1. Startup Diagram
Start
Wait 0.3 ms Start VDD3 Comparator
No
VIN > 2.7V ?
Yes Start LDO3 Start LDO2 Start LDO1
No
VIN < 2.6 V ?
Yes Wait 220 ms XRESO = 1 Wait 1 ms WRESO = XRESIN XRESO = 0 Wait 1 ms Stop LDO1, 2, 3
POR2, supplied by VDD3, resets the startup state machine. After 0.3 ms, the VDD3 comparator is started. If VDD3 is greater than 2.7V, LDO regulators are started in the following order: LDO3, LDO2, LDO1. During LDO regulator VDD startup, voltage is not checked. Then XRESO is kept grounded for 220 ms, tied high for 1 ms, before following XRESIN. During that state, VDD3 voltage is monitored and if it is lower than 2.6V, LDO regulators 1, 2 and 3 are stopped and XRESO is grounded. Both XRESIN and VDD3 comparator output are debounced at rising and falling edges for two 10 kHz clock cycles. Debounce time is typically between 100 s and 200 s. Timings are defined 40%.
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8. Normal Procedure
The State Machine monitors the XRESIN pin and provides the proper XRESO pin signal when reset occurs. Through the Two-wire Interface (TWI), the user can control and change the output voltage delivered by LDO1, LDO2, LDO3 and LDO4.
9. Two-wire Interface (TWI) Protocol
The two-wire interface interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds up to 400 Kbits per second, based on a byte oriented transfer format. The TWI is slave only and has single byte access. The TWI adds flexibility to the power supply solution, enabling LDO regulators to be controlled depending on the instantaneous application requirements. The AT73C239 has the following 7-bit address: 1001000. Attempting to read data from register addresses not listed in this section results in 0xFF being read out. * TWCK is an input pin for the clock * TWD is an open-drain pin driving or receiving the serial data The data put on TWD line must be 8 bits long. Data is transferred MSB first. Each byte must be followed by an acknowledgement. Each transfer begins with a START condition and terminates with a STOP condition. * A high-to-low transition on TWD while TWCK is high defines a START condition. * A low-to-high transition on TWD while TWCK is high defines a STOP condition. Figure 9-1. START and STOP Conditions
TWD
TWCK Start Stop
Figure 9-2.
Transfer Format
TWD
TWCK
Start
Address
R/W
Ack
Data
Ack
Data
Ack
Stop
After the host initiates a START condition, it sends the 7-bit slave address defined above to notify the slave device. A read/write bit follows (read = 1, write = 0).
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The device acknowledges each received byte. The first byte sent after the device address and the R/W bit, is the address of the device register the host wants to read or write. For a write operation the data follows the internal address. For a read operation a repeated START condition needs to be generated followed by a read on the device. Figure 9-3.
TWD
Write Operation
S ADDR W A IADDR A DATA A P
Figure 9-4.
TWD S
Read Operation
ADDR W A IADDR A S ADDR R A DATA N P
* S = Start * P = Stop * W = Write * R = Read * A = Acknowledge * N = Not Acknowledge * DADR= Device Address * IADR = Internal Address
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10. Normal Modes and Quiescent Current
Table 10-1. Normal Modes and Quiescent Current
Quiescent [A] Modes Backup Battery Conditions VBAT present, VDD3 not present typ 10 max 30
LDO4 on
VBAT present, VDD3 present
Normal
LDO4 on LDO1 on LDO2 on LDO3 on
800
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11. Electrical Characteristics
11.1 Absolute Maximum Ratings
Absolute Maximum Ratings
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 11-1.
Operating Temperature (Industrial).............. -40 C to +85 C Storage Temperature .................................. -55C to +150C Power Supply Input on VBAT .......................... -0.3V to + 3.6V Power Supply Input on VDD1,VDD2,VDD3 ....... -0.3V to + 3.6V Digital IO Input Voltage ................................. -0.3V to + 3.6V TWI IO Input Voltage .................................... -0.3V to + 5.5V All Other Pins................................................ -0.3V to + 3.6V
11.2
Recommended Operating Conditions
Recommended Operating Conditions
Condition Min -40 VDD1, VDD2, VDD3 VBAT 3.0 2.5 Max 85 3.6 3.6 Unit C V
Table 11-2.
Parameter
Operating Temperature Power Supply Input
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12. Timing Diagram
Figure 12-1. AT73C239 Timings
VBAT 1.5V
POR1 tSTART1 LDO4
VIN
1.5V
2.7V
2.6V
POR2
VMON tDELAY XRESIN
tRESGEN XRESO tSTARTHPBG HPBG
0.3 ms
tSTART2
LDO3 tSTART2
LDO2
tSTART2
LDO1
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At VDD3 startup XRESIN is taken into account only if it occurs after tDELAY. Table 12-1.
Parameter tSTART1 tSTART2 tSTARTHPBG tRESGEN tDELAY
Timing Parameters
Signal VO4 VO1,VO2, VO3 VBG XRESOUT Constraint LDO4 Startup time LDO1,2,3 Startup time HPBG startup time Delay to XRESOUT active 100 Min 10 10 Max 100 100 2 500 1 Unit sec sec ms ms ms
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13. Electrical Specification
13.1 LD01
LDO1 Parametric Table
Parameter Operating supply voltage Output voltage Load current Quiescent current Shutdown current Short circuit current Startup time Line regulation static Load regulation static Line regulation dynamic Load regulation dynamic From 3.0V to 3.6V From 10% to 100% I1 From 0 to 100% I1 From 3.1V to 3.6V tR = tF = 5 s, I1 = 5 mA From 10% to 100% I1, tR = tF = 5 s, Sine Wave, 100 kHz frequency, 3.3V mean 200 m vPP PSRR Power Supply Rejection Ratio Sine Wave, 10 kHz frequency, 3.3V mean, 200 m VPP Sine Wave, 1 kHz frequency, 3.3V mean 200 m VPP VOUT VN VNT StartUp Overshoot Output Noise Total Output Noise 10 Hz - 100 kHz 10 Hz - 100 kHz 2 2 7 2 2.5 48 55 60 40 45 55 HiZ output 200 100 Comments Switching Regulated Factory programmed Programmable Min 3.0 2.70 1.75 Typ 3.3 2.75 1.8 Max 3.6 2.80 1.85 25 300 1 Units V V V mA A A mA s mV mV mV mV dB dB dB mV VRMS VRMS
Table 13-1.
Symbol VDD1 VO1 I1 IQC ISC ISH tR VDC VDC VTRAN VTRAN
Table 13-2.
COUT1
LDO1 External Components
Description X5R 1 F 20% ceramic capacitor
Schematic Reference
Table 13-3.
onldo1 0 1 1
Control Modes
sel1 0 0 1 VO1 HiZ 2.75V 1.8V
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13.2
LDO2
LDO2 Parametric Table
Parameter Operating supply voltage Output voltage Load current Quiescent current Shutdown current Short circuit current Startup time Line regulation static Load regulation static Line regulation dynamic Load regulation dynamic From 3.0V to 3.6V From 10% to 100% I2 From 0 to 100% I2 From 3.1V to 3.6V tR = tF = 5 s, I2 = 30 mA From 10% to 100% I1, tR = tF = 5 s, Sine Wave, 100 kHz frequency, 3.3V mean 200 m VPP 2 2 3 2 3 40 50 70 30 10 Hz - 100 kHz 10 Hz - 100 kHz 35 45 HiZ output 200 100 Comments Switching Regulated Factory programmed Programmable Min 3.0 1.75 1.45 Typ 3.3 1.8 1.5 Max 3.6 1.85 1.55 30 300 1 Units V V V mA A A mA s mV mV mV mV dB dB dB mV VRMS VRMS
Table 13-4.
Symbol VDD2 V02 I2 IQC ISC ISH tR VDC VDC VTRAN VTRAN
PSRR
Power Supply Rejection Ratio
Sine Wave, 10 kHz frequency, 3.3V mean, 200 m VPP Sine Wave, 1 kHz frequency, 3.3V mean 200 m VPP
VOUT VN VNT
Startup Overshoot Output Noise Total Output Noise
Table 13-5.
External Components
Description X5R 1 F 20% ceramic capacitor
Schematic Reference COUT2
Table 13-6.
on2ldo 0 1 1
Control Modes
sel2 X 0 1 VO2 HiZ 1.8V 1.5V
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13.3 LDO3
LDO3 Parametric Table
Parameter Operating supply voltage Output voltage Load current Quiescent current Shutdown current Short circuit current Startup time Line regulation static Load regulation static Line regulation dynamic Load regulation dynamic From 3.0V to 3.6V From 10% to 100% I3 From 0 to 100% I3 From 3.1V to 3.6V tR = tF = 5 s, I3 = 60 mA From 10% to 100% I1, tR = tF = 5 s, Sine Wave, 100 kHz frequency, 3.3V mean 200 m VPP PSRR Power Supply Rejection Ratio Sine Wave, 10 kHz frequency, 3.3V mean, 200 m VPP Sine Wave, 1 kHz frequency, 3.3V mean 200 m VPP VOUT VN VNT Startup Overshoot Output Noise Total Output Noise 10 Hz - 100 kHz, without VBG 10 Hz - 100 kHz 2 2 3 2 3 40 50 70 30 35 45 HiZ output 200 100 Comments Switching Regulated Factory programmed VO3 I3 IQC ISC ISH tR VDC VDC VTRAN VTRAN Programmable Programmable Min 3.0 1.75 1.45 1.18 Typ 3.3 1.8 1.5 1.23 Max 3.6 1.85 1.55 1.28 60 300 1 Units V V V V mA A A mA s mV mV mV mV dB dB dB mV VRMS VRMS
Table 13-7.
Symbol VDD3
Table 13-8.
External Components
Description X5R 1 F 20% ceramic capacitor
Schematic Reference COUT3
Table 13-9.
onldo3 0 1 1 1
Control Modes
sel3[0] X 0 1 0 sel3[1] X 0 0 1 VO3 HiZ 1.8V 1.5V 1.23V
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13.4
LDO4
LDO4 generates 1.2V, 1.5V or 1.8V voltage from VBAT supply. Max DC load is 2 mA. The regulator is activated when POR1 is released.
Table 13-10. LDO4 Parametric Table
Symbol VBAT VO4 I4 IQC ISC tS VDC VDC Parameter Operating supply voltage Conditions Backup Battery or Supercap Factory programmed Output voltage Programmable Programmable Load current Quiescent current Shutdown current Startup time Line regulation static Load regulation static 2.5V < VBAT < 3.6V 0 < I4 < 2 mA DC load current 3 Min 2.5 1.7 1.4 1.1 1.8 1.5 1.2 Typ Max 3.6 1.9 1.6 1.3 2 5 0.5 200 100 100 Unit V V V V mA A A s mV mV
Table 13-11. LDO4 External Components
Schematic Reference COUT4 Description X5R 1 F 20% capacitor
Table 13-12. onldo4 sel4[1:0] Control Modes
onldo4 0 1 1 1 sel4<1> X 0 0 1 sel4<0> X 0 1 0 VO4 HiZ 1.8V 1.5V 1.2V
Table 13-13. trcore[1:0] Control Modes
trcore<1> 0 0 1 1 trcore<0> 0 1 0 1 VO4 typ + 8 0mV - 80 mV
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13.5 High Performance Bandgap (HPBG)
Table 13-14. HPBG Parametric Table
Symbol VBG ISC IQC tS VN PSRR Parameter Output voltage Shutdown current Quiescent current Startup time Output noise Power Supply Rejection Ratio CF= 100 nF BW 10 Hz to 100 kHz F = 100 Hz 1 7 65 Conditions Factory trimmed encore = en = 0, dcrun = 0 (1) Min Typ 1.231 1 6 30 2 Max Units V A A ms VRMS dB
Table 13-15. External Components
Schematic Reference CF Description X5R 100 nF 20% ceramic capacitor minimum
13.6
Low Power Bandgap (LPBG)
Table 13-16. LPBG Parametric Table
Symbol VBAT IQC tS VLPBG Parameter Operating supply voltage Quiescent current Startup time Bandgap Voltage 1.15 1.2 Conditions Backup Battery or Supercap Min 2.5 4 Typ Max 3.6 7.5 100 1.25 Unit V A s V
13.7
Power On Reset on VBAT (POR1)
Table 13-17. POR1 Parametric Table
Symbol VBAT IQC VPON VPOFF Parameter Operating supply voltage Quiescent current POR1 on threshold POR1 off threshold Conditions Backup Battery or Supercap Min 2.5 3 1.45 1.5 Typ Max 3.6 Unit V A V V
13.8
Power On Reset on VDD3 (POR2)
Table 13-18. POR2 Parametric Table
Symbol VDD3 IQC VPON VPOFF Parameter Operating supply voltage Quiescent current POR2 on threshold POR1 off threshold Conditions Switching regulated Min 0 3 1.45 1.5 Typ Max 3.6 Unit V A V V
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13.9
Voltage Monitor
Table 13-19. Voltage Monitor Parametric Table
Symbol IQC VPON VPOFF Parameter Quiescent current POR2 on threshold POR1 off threshold on VDD3 on VDD3 2.7 2.6 Conditions Min Typ Max 20 2.72 2.60 Unit A V V
13.10 XRESIN
Table 13-20. XRESIN Parametric Table
Symbol VI Parameter Input supply voltage range Conditions driven by CPU GPIO driven by CPU open drain output connected to VDD3 when not used Min 1.8 Hiz VDD3 Typ Max 3.3 Unit V V V
13.11 XRESO
Table 13-21. XRESO Parametric Table
Symbol VI Parameter Input supply voltage range Conditions Min 1.8 Typ Max 3.3 Unit V
13.12 TWICK
Table 13-22. TWICK Parametric Table
Symbol VI Parameter Input supply voltage range Conditions Min 1.8 Typ Max 5.5 Unit V
13.13 TWID
Table 13-23. TWID Parametric Table
Symbol VI Parameter Input supply voltage range Conditions Min 1.8 Typ Max 5.5 Unit V
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14. AT73C239 User Interface
Table 14-1.
Offset 0x00 0x08 0x0A
AT73C239 Register Mapping
Register LDO_CTRL LDO_TRIM1 LDO_TRIM4 Register Description LDO Control LDO 1,2,3 Trim LDO4 Trim Access Read/Write Read/Write Read/Write Reset Value 0x0F 0x00 0x00
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14.1
LDO Control Register
LDO_CTRL 0X0F Read/Write
Register Name: Reset State: Access:
7 -
6 -
5 -
4 -
3 Onldo4
2 Onldo3
1 Onldo2
0 Onldo1
* Onldo1: LDO1 enable (active high) reset value = 1. * Onldo2: LDO2 enable (active high) reset value = 1. * Onldo3: LDO3 enable (active high) reset value = 1. * Onldo4: LDO4 enable (active high) reset value = 1.
14.2
LDO 1, 2, 3 Trim Register
LDO_TRIM1 0X08 Read/Write
Register Name: Reset State: Access:
7 -
6 -
5 -
4 Sel1
3 Sel2
2 Sel3
1
0 -
* Sel3 LDO3 output voltage select, reset = 00 * Sel2 LDO2 output voltage select, reset = 0 * Sel1 LDO1 output voltage select, reset = 0
Sel1 0 1
VO1 2.75V 1.8V
Sel2 0 1
VO2 1.8V 1.5V
Sel3 00 01 10 11
VO3 1.8V 1.5V 1.23V 1.8V
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AT73C239
14.3 LDO 4 Trim Register
LDO_TRIM4 0X0A Read/Write Register Name: Reset State: Access:
7 -
6 -
5 -
4 -
3 Sel4
2
1 -
0 -
* Sel4 LDO4 output voltage select, reset = 00
Sel4 00 01 10 11
VO4 1.8V 1.5V 1.2V 1.2V
27
6201C-PMAAC-31-Jul-07
15. Package Information
Figure 15-1. Mechanical Package Drawing for 16-lead Quad Flat No Lead Package
Note:
All dimensions are in mm.
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AT73C239
6201C-PMAAC-31-Jul-07
AT73C239
16. Ordering Information
Table 16-1. Ordering Information
Package QFN3x3 mm Package Type Green Temperature Operating Range 0C to +70C
Ordering Code AT73C239
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6201C-PMAAC-31-Jul-07
Revision History
Doc. Rev 6201A Date 01-Sep-05 11-Oct-05 Comments First issue Unqualified on Intranet Changed HPBG minimum requirement information in Change Request Ref.
6201B
03-Mar-06
Section 6.5 "High Performance Bandgap (HPBG)" on page 9. Updated Figure 7-1 on page 12 with new values. Updated Figure 12-1 on page 17 with new
information for LDO2 and LDO3 signals. Updated Table 13-14, "HPBG Parametric Table," on page 23 with max value for startup time and changed condition.
2472
6201C
09-Jul-07
Added Section 4. "Package" on page 4.
4591
30
AT73C239
6201C-PMAAC-31-Jul-07
Headquarters
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International
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Product Contact
Web Site www.atmel.com www.atmel.com/PowerMgmnt Technical Support pmaac@atmel.com Sales Contacts www.atmel.com/contacts/
Literature Requests www.atmel.com/literature
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6201C-PMAAC-31-Jul-07

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